The present invention pertains to a frequency synthesizer. In particular, the present invention pertains to a frequency synthesizer that can correctly compensate for ripple current.
Frequency-division multiple channel access systems are used in cellular telephones. In order to shift the transmission frequency to an empty channel, a frequency synthesizer capable of high-speed locking is required.
Reference numeral (101) in FIG. 7 represents a conventional frequency synthesizer. A PLL (phase-locked loop) circuit of the fractional frequency-division type is used.
Said frequency synthesizer (101) is arranged in a semiconductor integrated circuit device which constitutes the sending/receiving circuit of a cellular phone. The frequency synthesizer comprises oscillator (131), frequency divider (132), reference clock signal generator (133), phase comparator (134), charge pump circuit (135), low-pass filter (136), compensation circuit (137), and control circuit (138). Oscillator (131) outputs an external output signal OUT. The external output signal OUT is input to frequency divider (132) and other circuits in the semiconductor integrated circuit device where said frequency synthesizer (101) is arranged.
Frequency divider (132) divides the frequency at the input external output signal OUT, generates a comparison signal; and then outputs the comparison signal. Said phase comparator (134) compares the phase of the comparison signal input from frequency divider (132) with the phase of the reference lock signal input from reference clock signal generator (133), controls charge pump circuit (135), and generates a control signal. The control signal is output to oscillator (131) via low-pass filter (136).
Oscillator (131) operates in such a way that the frequency of the external output signal OUT is varied according to the input control signal to make the phase of the comparison signal consistent with the phase of the reference clock signal. As a result, the frequency of the external output signal OUT becomes higher than the frequency of the reference clock signal by a multiple of the frequency division value of frequency divider (132).
Said frequency divider (132) is controlled by control circuit (138) so that its frequency division value varies periodically. For example, if the frequency of the reference clock signal is 200 kHz and the frequency division value is 5000 for seven clock cycles (35 xcexcsec) and 5001 for one clock cycle (5 xcexcsec), the average frequency division value obtained by averaging over eight clock cycles will be 5000.125 (=5000+xe2x85x9). The frequency of the external output signal OUT becomes 1000025 kHz, which is higher than the frequency of the reference clock signal by a multiple of the average frequency division value.
If the frequency division value is 4000 for six of eight cycles and is 4001 for the other two, the average frequency division value will be 4000.25, and the frequency of the external output signal OUT will be 800.050 MHz.
If the average frequency division value has a fractional part, it becomes possible to use a high frequency, such as 800 MHz or 1 GHz, in a narrow channel interval, such as 25 kHz or 12.5 kHz.
However, if the frequency division value is varied periodically as described above, even if after the external output signal OUT is locked to a desired frequency, a phase difference will occur due to inconsistency between the phase between the comparison signal and the reference clock signal. As a result, ripple current appears in the control signal output from charge pump circuit (135).
Reference symbol a in FIG. 8 indicates the waveform of the comparison signal output from frequency divider (132) after the external output signal OUT is locked when the frequency division value is varied by N and N+1. Reference symbol b indicates the waveform of the reference clock signal. Reference symbol c indicates the waveform of the ripple current included in the control signal output from charge pump circuit (135) as a result of inconsistency between the phase of the comparison signal relative to the reference clock signal.
The ripple current included in the control circuit [sic; signal] will cause a spurious component to appear in the external output signal OUT. Therefore, the ripple current not only impairs the receiving performance of the cellular phone or another telecommunication device but also acts as a source of interference during communication. This is a very serious problem.
A compensation circuit (137) having D/A converter (141) and capacitor (142) is arranged in said frequency synthesizer (101). D/A converter (141) varies the voltage applied to capacitor (142) to generate a compensation current of opposite polarity and the same amount of charge as the ripple current. The compensation current is superimposed on the control signal output from charge pump circuit (135) to cancel the ripple current. As a result, an external output signal OUT without the spurious component is obtained.
The amount of charge in the ripple current varies with time in such a way that it is an integer multiple of a certain amount of unit charge. The amount of unit charge is the product of the phase difference between the comparison signal and reference clock signal and the output current of the charge pump circuit. In the example described above, the frequency of the external output signal OUT was 1000025 kHz; if the output current of charge pump circuit (135) is a constant current of +1 mA or xe2x88x921 mA, the following Qr
Qr=(xe2x85x9)xc3x97(1/1000025 kHz)xc3x971 mAxc3x97xc2xd=62.5xc3x9710xe2x88x9215 (Coulomb)xe2x80x83xe2x80x83(101)
becomes the amount of unit charge.
The aforementioned compensation current with a charge amount in the range of xc2x11 time to a maximum of xc2x17 times (xc2x1Qr) the amount of unit charge Qr is generated with the same period as the reference clock signal in the sequence of
+7Qrxe2x86x92+5Qrxe2x86x923Qrxe2x86x92+1Qrxe2x86x92xe2x88x921Qrxe2x86x92xe2x88x923Qrxe2x86x92xe2x88x925Qrxe2x86x92xe2x88x927Qr
In order to compensate for the ripple current, with the capacitance of capacitor (142) taken as Ct, if voltage Ve which satisfies the following equation
Ctxc2x7Vc=Qrxe2x80x83xe2x80x83(102)
is used as the unit and the output voltage is varied as xe2x88x927Ve, xe2x88x925Ve, xe2x88x923Ve, xe2x88x921Ve, +1Ve, +3Ve, +5Ve, and +7Ve by D/A converter (141), a compensation current with the opposite polarity and the same amount of charge as the ripple current can be generated.
However, as can be seen from said equation (101), the amount of the ripple current is proportional to the output current of charge pump circuit (135). Since the output current varies as a function of temperature, etc., the-ripple current cannot be compensated.
The general object of the present invention is to solve the aforementioned problems of the conventional technology by providing a technology which can correctly compensate for the ripple current.
This and other objects and features are provided by one aspect of the present invention by a frequency synthesizer comprising an oscillator that controls the frequency of an oscillation signal with an appropriate control signal, a frequency divider of the fractional frequency division type that frequency-divides the aforementioned oscillation signal and generates a comparison signal, a reference clock signal generator that generates a reference clock signal, a phase comparator that compares the phase of the aforementioned comparison signal with the phase of the aforementioned reference clock signal and outputs a phase difference signal, a charge pump circuit that outputs a current corresponding to the aforementioned phase difference signal, a low-pass filter that removes the high-frequency component of the current output from the aforementioned charge pump circuit and supplies its output as the conventional control signal to the aforementioned oscillator, and a compensation circuit that supplies a compensation current used for compensating the ripple current included in the aforementioned control signal to the output terminal of the aforementioned charge pump circuit; wherein the aforementioned frequency divider includes a prescaler which performs frequency dividing for the aforementioned oscillation signal and a counter that is operated corresponding to the output signal of the aforementioned prescaler to output the aforementioned comparison signal; and the aforementioned compensation current is determined on the basis of one of the frequency division values of the aforementioned prescaler which varies periodically, one period of the aforementioned frequency division value which varies periodically, and the time period of the aforementioned frequency division value.
Another aspect of the invention includes a frequency synthesizer having a correction circuit that includes a detection capacitor connected to the aforementioned charge pump circuit and is able to generate a reference voltage from the voltage of the aforementioned detection capacitor. The aforementioned compensation circuit includes a voltage generator that outputs a voltage corresponding to the aforementioned reference voltage, and a compensation capacitor connected between the aforementioned voltage generator and the output terminal of the aforementioned charge pump circuit. The capacitance ratio of the aforementioned detection capacitor to the compensation capacitor is determined on the basis of one of the frequency division values of the aforementioned prescaler that varies periodically, one period of the aforementioned frequency division value that varies periodically, and the time period of the aforementioned frequency division value. The aforementioned correction circuit charges/discharges the aforementioned detection capacitor with the output current of the aforementioned charge pump circuit only during the time period of one of the frequency division values of the aforementioned prescaler, and the aforementioned reference voltage is generated from the voltage of the aforementioned detection capacitor obtained by means of said charging/discharging.
A further aspect of the invention is provided by a the frequency synthesizer in which the time difference between charging and discharging of the aforementioned detection capacitor is set as the time for one period of the aforementioned oscillation signal whose frequency has been divided with one of the aforementioned frequency division values. The aforementioned detection capacitor is charged or discharged twice, and the aforementioned reference voltage is generated from the voltage of the detection capacitor obtained in that way.
Yet another aspect of the invention includes a voltage generator of the frequency synthesizer which outputs a voltage that is an integer multiple of the aforementioned reference voltage to the aforementioned compensation capacitor.
As described above, according to one aspect of the present invention, the frequency of the oscillation signal output from the oscillator is divided while the frequency division value is varied periodically by the prescaler in the frequency divider, and the counter operates correspondingly to generate a comparison signal. The comparison signal and the reference clock signal are input to the phase comparator.
The charge pump circuit of one aspect of the invention is operated by the phase comparator which compares the phase of the comparison signal relative to the input reference clock signal. A constant current is output from the charge pump circuit corresponding to the phase difference. After the high-frequency component is removed from the current with the low-pass filter, a control signal is obtained.
The control signal output from the low-pass filter of one aspect of the invention is input to the oscillator. The oscillator varies the frequency of the oscillation signal on the basis of the control signal. As a result, the frequency of the oscillation signal becomes higher than the frequency of the reference clock signal by a multiple of the average frequency division value. In this way, the frequency of the oscillation signal is increased, and the channel interval is reduced.
A compensation circuit of one aspect of the invention is arranged in the frequency synthesizer to generate a compensation current opposite in sign to the ripple current that appears in the control signal. Since the compensation current is superimposed on the control signal, the ripple current that appears in the control signal is cancelled out, and the spurious oscillation signal component is eliminated.
However, if the amount of charge in the ripple current varies and becomes inconsistent with the compensation current, the ripple current cannot be cancelled out correctly.
Therefore, a frequency synthesizer which makes the amount of the compensation current follow the variation in the amount of the output current of the charge pump circuit is proposed as one aspect of the present invention. Since the amount of charge in the ripple current is proportional to the amount of the output current of the charge pump circuit, once the reference charge amount becomes consistent with the amount of charge in the ripple current, the compensation current can follow the variation in the ripple current, if any exists. Consequently, the amount of charge in the compensation current can be kept equal to the amount of charge in the ripple current correctly and with only the opposite polarity.
The compensation circuit of the frequency synthesizer of one aspect of the invention has a compensation capacitor and a voltage generator. One end of the compensation capacitor is connected to the output end of the charge pump circuit, and the other end is connected to the voltage generator. The voltage applied to the compensation capacitor is varied on the basis of the reference voltage input to the voltage generator to generate a compensation current. The reference voltage is supplied from a correction circuit. The correction circuit has a detection capacitor which is charged/discharged by the charge pump circuit. The voltage of the detection capacitor is output as the reference voltage. In this way, the amount of compensation current can follow the amount of output current of the charge pump circuit. As a result, the amount of charge in the compensation current can be made to follow the amount of charge in the ripple current.
However, the unit amount of charge in the ripple current is expressed as the product of the phase difference between the comparison signal and the reference clock signal and the output current of the charge pump circuit. The amount of charge in the ripple current varies as an integer multiple of the amount of unit charge for the same period as the reference clock signal.
As a result, if the charge/discharge time of the detection capacitor is set regardless of the oscillation signal, which is related to the unit charge in the ripple current, when the period of the oscillation signal varies, then the charge/discharge time does not change following the variation in the oscillation signal, nor does the charge on the detection capacitor change as a result of charging/discharging.
Consequently, the amount of the compensation determined by the charge on the detection capacitor as a result of charging/discharging cannot follow the amount of the output current after the oscillation signal is varied. As a result, the amount of charge in the compensation current cannot follow the amount of charge in the ripple current to cancel the ripple current.
In one aspect of the present invention, however, if the reference voltage is determined, the capacitance ratio between the detection capacitor and the compensation capacitor is determined on the basis of one of the frequency division values of the aforementioned prescaler which varies periodically, one period of the aforementioned frequency division value which varies periodically, and the time period of the aforementioned frequency division value. The detection capacitor which satisfies the capacitance ratio is charged/discharged by the output current of the charge pump circuit only during the time of one period of the prescaler, and the reference voltage is generated from the voltage appearing at the two ends of the detection capacitor during charging/discharging.
Therefore, when the period of the oscillation signal varies, the reference voltage also changes correspondingly.
In the compensation circuit of one aspect of the invention, a voltage generator outputs a voltage corresponding to the reference voltage to the compensation capacitor, and a compensation current is generated when the compensation capacitor is charged/discharged. Therefore, when the reference voltage changes, the amount of compensation current also changes. The compensation current can follow the variation in the amount of the output current of the charge pump circuit which causes the variation in the oscillation signal.
Consequently, even if the oscillation signal varies, the amount of charge in the compensation current can follow the amount of charge in the ripple current, and the ripple current can be cancelled out correctly.
Also, the charge/discharge time of the detection capacitor in one aspect of the invention is varied. The difference between various charge/discharge times is set to be equal to one period of the aforementioned oscillation signal whose frequency has been divided by one of the frequency division values. The detection capacitor is charged/discharged at least twice. The voltage across the detection capacitor during each charge/discharge cycle is stored, and the reference voltage is obtained from this voltage difference. In this way, the error in the voltage value caused by the difference in time, which is taken by the switch that controls charging/discharging to change from the conductive state to the cut-off state, and the time taken by the switch to change from the cut-off state to the conductive state can be eliminated from the reference voltage. Consequently, the amount of charge in the compensation current can be made equal (with opposite polarity) to the amount of charge in the ripple current.